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QL3025 pASIC 3 FPGA Data Sheet
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25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
* 25,000 Usable PLD Gates with 204 I/Os * 300 MHz 16-bit Counters,
Four Low-Skew Distributed Networks
* Two array clock/control networks available
400 MHz Datapaths * 0.35 m four-layer metal non-volatile CMOS process for smallest die sizes
Easy to Use / Fast Development Cycles
* 100% routable with 100% utilization and
to the logic cell flip-flop clock, set and reset inputs -- each driven by an input-only pin * Two global clock/control networks available to the logic cell; F1, clock set, reset inputs and the input, I/O register clock, reset, and enable inputs as well as the output enable control -- each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback
complete pin-out stability * Variable-grain logic cells provide high performance and 100% utilization * Comprehensive design tools include high quality Verilog/VHDL synthesis
High Performance
* Input + logic cell + output total delays
under 6 ns * Data path speeds over 400 MHz * Counter speeds over 300 MHz
Advanced I/O Capabilities
* Interfaces with both 3.3 V and 5.0 V devices * PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades * Full JTAG boundary scan * I/O Cells with individually controlled Registered Input Path and Output Enables
Total of 204 I/O Pins
* 196 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades * Four High Drive input-only pins * Four High Drive input-only/distributed network pins
Figure 1: 672 pASIC 3 Logic Cells
(c) 2002 QuickLogic Corporation
www.quicklogic.com
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QL3025 pASIC 3 FPGA Data Sheet Rev E
Architecture Overview
The QL3025 is a 25,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 m four-layer metal process using QuickLogic's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL3025 contains 672 logic cells. With a maximum of 204 I/Os, the QL3025 is available in 144-pin TQFP, 208-pin PQFP, and 256-pin PBGA packages. Software support for the complete pASIC 3 family, including the QL3025, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation.
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(c) 2002 QuickLogic Corporation
QL3025 pASIC 3 FPGA Data Sheet Rev E
Electrical Specifications
AC Characteristics at VCC = 3.3 V, TA = 25C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 7 by the numbers provided in Table 1 through Table 5.
Table 1: Logic Cells Symbol Parameter 1 tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delay Setup Time b Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width
b
Propagation Delays (ns) Fanouta 2 1.7 1.7 0.0 1.0 1.2 1.2 1.3 1.1 1.9 1.8 3 1.9 1.7 0.0 1.2 1.2 1.2 1.5 1.3 1.9 1.8 4 2.2 1.7 0.0 1.5 1.2 1.2 1.8 1.6 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7. b. These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
Table 2: Input-Only/Clock Cells Symbol Parameter 1 tIN tINI tISU tIH tlCLK tlRST tlESU tlEH High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout a 2 1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0 3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0 4 1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0 8 2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0 12 2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7.
(c) 2002 QuickLogic Corporation
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QL3025 pASIC 3 FPGA Data Sheet Rev E
Table 3: Clock Cells Symbol Parameter Propagation Delays (ns) Loads per Half Column a 1 tACK tGCKP tGCKB Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1.2 0.7 0.8 2 1.2 0.7 0.8 3 1.3 0.7 0.9 4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 1.6 0.7 1.2 11 1.7 0.7 1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to eight loads per half column. The global clock has up to 11 loads per half column.
Table 4: Input-Only I/O Cells Symbol Parameter Propagation Delays (ns) Fanout a 1 tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.3 3.1 0.0 0.7 0.6 2.3 0.0 2 1.6 3.1 0.0 1.0 0.9 2.3 0.0 3 1.8 3.1 0.0 1.2 1.1 2.3 0.0 4 2.1 3.1 0.0 1.5 1.4 2.3 0.0 8 3.1 3.1 0.0 2.5 2.4 2.3 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7.
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(c) 2002 QuickLogic Corporation
QL3025 pASIC 3 FPGA Data Sheet Rev E
Table 5: Output-Only I/O Cells Symbol Parameter 30 tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State Output Delay Low to Tri-State
a
Propagation Delays (ns) Output Load Capacitance (pF) 50 2.5 2.6 1.7 2.0 75 3.1 3.2 2.2 2.6 100 3.6 3.7 2.8 3.1 150 4.7 4.8 3.9 4.2 -
2.1 2.2 1.2 1.6 2.0 1.2
a. The following loads presented in Figure 2 are used for tPXZ:
tPHZ 1 5 pF
1 tPLZ 5 pF
Figure 2: Loads used for tPXZ
(c) 2002 QuickLogic Corporation
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QL3025 pASIC 3 FPGA Data Sheet Rev E
DC Characteristics
The DC specifications are provided in Table 6 through Table 8.
Table 6: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity Value -0.5 V to 4.6 V -0.5 V to 7.0 V -0.5 V to VCCIO +0.5 V 200 mA Parameter DC Input Current ESD Pad Protection Storage Temperature Lead Temperature Value 20 mA 2000 V -65C to +150C 300C
Table 7: Operating Range Symbol Parameter Military Min VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade -1 Speed Grade K Delay Factor -2 Speed Grade -3 Speed Grade -4 Speed Grade 3.0 3.0 -55 0.42 0.42 Max 3.6 5.5 125 1.64 1.37 Industrial Min 3.0 3.0 -40 0.43 0.43 0.43 0.43 0.43 Max 3.6 5.5 85 1.90 1.54 1.28 0.90 0.82 Commercial Min 3.0 3.0 0 0.46 0.46 0.46 0.46 0.46 Max 3.6 5.25 70 1.85 1.50 1.25 0.88 0.80 V V C C n/a n/a n/a n/a n/a Unit
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(c) 2002 QuickLogic Corporation
QL3025 pASIC 3 FPGA Data Sheet Rev E
Table 8: DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOH = -12 mA IOH = -500 A IOL = 16 mAa IOL = 1.5 mA VI = VCCIO or GND VI = VCCIO or GND -10 -10 Conditions Min 0.5 VCC -0.5 2.4 0.9 VCC 0.45 0.1 VCC 10 10 10 VO = GND VO = VCC VI, VIO = VCCIO or GND -15 40 0.50 (typ) 0 -180 210 2 100 Max VCCIO + 0.5 0.3 VCC Units V V V V V V A A pF mA mA mA A
VOL II IOZ CI IOS ICC ICCIO
Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitanceb Output Short Circuit Currentc D.C. Supply Current
d
D.C. Supply Current on VCCIO
a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. b. Capacitance is sample tested only. Clock pins are 12 pF maximum. c. Only one output at a time. Duration should not exceed 30 seconds. d. For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer applications group. (See Contact Information).
(c) 2002 QuickLogic Corporation
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QL3025 pASIC 3 FPGA Data Sheet Rev E
Kv and Kt Graphs
Voltage Factor vs. Supply Voltage
1.1000 1.0800 1.0600 1.0400
Kv
1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V)
Figure 3: Voltage Factor vs. Supply Voltage
Temperature Factor vs. Operating Temperature
1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80
Kt
Junction Temperature C
Figure 4: Temperature Factor vs. Operating Temperature
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(c) 2002 QuickLogic Corporation
QL3025 pASIC 3 FPGA Data Sheet Rev E
Power-up Sequencing
VCCIO
Voltage
VCC (VCCIO -VCC)MAX VCC
400 us
Time
Figure 5: Power-up Requirements
The following requirements must be met when powering up the device (refer to Figure 5): this recommendation can cause permanent damage to the device. * VCCIO must lead VCC when ramping the device. * The power supply must take greater than or equal to 400 s to reach VCC. Ramping to VCC/VCCIO earlier than 400 s can cause the device to behave improperly. An internal diode is present in-between VCC and VCCIO, as shown in Figure 6.
V CC V CCIO
* When ramping up the power supplies keep (VCCIO -VCC)MAX 500 mV. Deviation from
Internal Logic Cells, RAM blocks, etc
IO Cells
Figure 6: Internal Diode Between VCC and VCCIO
(c) 2002 QuickLogic Corporation
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QL3025 pASIC 3 FPGA Data Sheet Rev E
JTAG
TCK TMS TRSTB TAp Controller State Machine (16 States) Instruction Decode & Control Logic
Instruction Register
RDI
Mux Boundary-Scan Register (Data Register)
Mux
TDO
Bypass Register
Internal Register
I/O Registers
User Defined Data Register
Figure 7: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements.
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(c) 2002 QuickLogic Corporation
QL3025 pASIC 3 FPGA Data Sheet Rev E
The 1149.1 standard requires the following three tests:
* Extest Instruction. The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. * Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device.
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QL3025 pASIC 3 FPGA Data Sheet Rev E
Pin Descriptions
Table 9: Pin Descriptions Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC VCCIO GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode Description Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation.
High-drive input and/or array Can be configured as either or both. network driver High-drive input and/or global Can be configured as either or both. network driver High-drive input Input/Output pin Power supply pin Input voltage tolerance pin Ground pin Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3 V supply. Connect to 5.0 V supply if 5 V input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground.
Ordering Information
QL 3025 - 1 PQ208 C QuickLogic device pASIC 3 device part number Speed Grade 0 = Quick 1 = Fast 2 = Faster 3 = Faster *4 = Wow Operating Range C = Commercial I = Industrial M = Military Package Code PF144 = 144-pin TQFP PQ208 = 208-pin PQFP PB256 = 256-pin PBGA
* Contact QuickLogic regarding availability. (See Contact Information)
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(c) 2002 QuickLogic Corporation
QL3025 pASIC 3 FPGA Data Sheet Rev E
144 TQFP Pinout Diagram
Pin 1 Pin 109
pASIC 3 QL3025-1PF144C
Pin 37
Pin 73
Figure 8: Top View of 144 Pin TQFP
208 PQFP Pinout Diagram
Pin 157
Pin 1
pASIC 3 QL3025-1PQ208C
Pin 53
Pin 105
Figure 9: Top View of 208 Pin PQFP
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QL3025 pASIC 3 FPGA Data Sheet Rev E
144 TQFP & 208 PQFP Pinout Table
Table 10: 144 TQFP & 208 PQFP Pinout Table
208 PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 144 TQFP NC 1 2 3 NC 4 5 NC 6 7 NC NC 8 NC 9 NC 10 11 12 13 NC 14 15 16 17 18 19 20 21 22 23 NC 24 NC 25 NC 26 27 28 NC NC 29 Function
I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O
208 PQFP 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
144 TQFP 30 31 NC 32 NC 33 NC 34 35 36 37 38 39 NC 40 NC NC 41 42 43 NC 44 45 NC 46 47 48 NC 49 NC 50 51 52 NC 53 54 55 56 NC 57 58 59
Function
GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O
208 PQFP 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
144 TQFP 60 61 NC 62 63 NC NC 64 NC 65 66 67 NC NC 68 69 NC 70 71 72 NC 73 NC 74 75 76 77 NC 78 79 80 NC 81 82 NC 83 NC 84 85 NC 86 NC
Function
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
208 PQFP 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
144 TQFP 87 88 89 90 91 92 93 94 95 NC 96 NC 97 98 NC 99 NC 100 NC 101 102 103 104 NC 105 106 NC 107 NC 108 109 110 111 NC 112 113 NC NC 114 115 116 NC
Function
GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O GND I/O VCC I/O I/O I/O
208 PQFP 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
144 TQFP 117 118 119 120 NC NC 121 NC 122 123 124 NC 125 126 127 128 129 NC 130 131 132 NC 133 134 NC 135 136 NC 137 NC 138 139 NC 140 NC 141 142 NC 143 144
Function
I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO I/O
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(c) 2002 QuickLogic Corporation
QL3025 pASIC 3 FPGA Data Sheet Rev E
256 PBGA Pinout Diagram
pASIC 3 QL3025-1PB256C
BOTTOM View
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER
Figure 10: 256-Pin PBGA Pinout Diagram
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QL3025 pASIC 3 FPGA Data Sheet Rev E
256 PBGA Pinout Table
Table 11: 256 PBGA Pinout Table
256 PBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 Function
VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC STM NC I/O I/O I/O I/O
256 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18
Function
I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VSS I/O VCC I/O VSS I/O I/O VCC I/O VSS I/O VCC I/O VSS I/O I/O I/O NC I/O I/O I/O I/O I/O
256 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1
Function
I/O I/O I/O I/O I/O VCC VCC NC I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O VSS VSS I/O I/O I/O I/O I/O NC I/O NC I/O I/O GCLK / I I/O I/O I/O VCC I ACLK / I I NC I
256 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4
Function
ACLK / I I GCLK / I VCC I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O VSS VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O VCC VCC I/O I/O I/O NC I/O I/O NC
256 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
Function
I/O I/O NC I/O I/O I/O I/O VSS I/O VCC I/O VSS I/O VCC I/O I/O VSS I/O VCC I/O VSS I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O TMS
256 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
Function
I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC
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(c) 2002 QuickLogic Corporation
QL3025 pASIC 3 FPGA Data Sheet Rev E
Contact Information
Telephone: 408 990 4000 (US) 416 497 8884 (Canada) 44 1932 57 9011 (Europe) 49 89 930 86 170 (Germany) 852 8106 9091 (Asia) 81 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com support@quicklogic.com http://www.quicklogic.com/
Revision History
Table 12: Revision History Revision A B C D E Date not avail. not avail. not avail May 2001 June 2002 Update of AC/DC Specs and reformat Added Kfactor, Power-up, JTAG and mechanical drawing information. Reformatted. Comments First release.
Copyright Information
Copyright (c) 2002 QuickLogic Corporation. All Rights Reserved. The information contained in this product brief, and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic, QuickWorks, pASIC, and ViaLink are registered trademarks of QuickLogic Corporation. Verilog is a registered trademark of Cadence Design Systems, Inc. All trademarks and registered trademarks are the property of their respective owners.
(c) 2002 QuickLogic Corporation
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